Generally, a NAND type flash memory device consists of a plurality of cell blocks. Each of the cell blocks includes a plurality of cell strings to which a plurality of cells are serially connected, a plurality of bit lines, a plurality of word lines, drain select transistors connected between the cell strings and the bit lines, and source select transistors connected between the cell strings and a common source line. Meanwhile, a plurality of memory cells which share one word line constitutes one page, and all the cells share a P well. The memory cell further includes a pass transistor for supplying a predetermined voltage to the cell block. The pass transistor includes a high voltage transistor for drain select, a high voltage transistor for source select and a high voltage transistor for cell select.
In the NAND type flash memory device constructed above, in order to program data into memory cells, an erase operation is first performed and a program operation is then effected to only selected cells. However, the program operation on the NAND type flash memory device is carried out in a page unit but the erase operation is performed in a cell block unit because all the cells share the P well. A conventional method of erasing the NAND type flash memory device will be below described in short.
One of a plurality of cell blocks is selected. A power supply voltage is then applied to the gate terminal of each of a high voltage transistor for drain select, a high voltage transistor for source select and a high voltage transistor for cell select within a pass transistor connected to the selected cell block. Next, a voltage of 4.5V is applied to a drain select transistor and a source select transistor through the high voltage transistor for drain select and the high voltage transistor for source select. A voltage of 0V is then applied to a memory cell through the high voltage transistor for cell select. Furthermore, a voltage of 0V is applied to the gate terminal of each of a high voltage transistor for drain select, a high voltage transistor for source select and a high voltage transistor for cell select within a pass transistor connected to a non-selected cell block. In addition, an erase voltage is applied to the P well of the entire cell blocks. In the P well of the non-selected cell, however, when a voltage of the P well rises to the erase voltage, a voltage of word lines of anon-selected cell block increases because of a coupling effect by capacitance of the word lines and capacitance between the word lines and the P well. Accordingly, the non-selected cell block is not erased.
In the conventional NAND type flash memory device in which the erase is effected in the cell block unit as described above, even when only a selected page has to be erased so as to program only the selected page, one cell block has to be all erased. Accordingly, there is a problem in that efficiency in terms of data management is significantly lowered.